digraph L1D_Final_Design_V2 {
rankdir=TB; // Top to Bottom layout
node [shape=box, style=filled, fillcolor=lightblue, fontname="Helvetica"];
edge [fontname="Helvetica", fontsize=10];
// 1. CPU Core Interface (LSU & MMU)
subgraph cluster_cpu_interface {
label="CPU Core Interface";
color=purple;
node [fillcolor=plum];
LSU [label="LSU (Load/Store Unit)"];
MMU_TLB [label="MMU & TLB\n(Memory Management Unit\n& Translation Lookaside Buffer)"];
LSU -> MMU_TLB [label="Virtual Address (VA)"];
MMU_TLB -> LSU [label="Physical Address (PA),\nPermissions, Cache Attributes"];
MMU_TLB -> LSU [label="Memory Access Exception", color=red, fontcolor=red];
}
// 2. L1D Cache Detailed Design
subgraph cluster_l1d_cache {
label="L1D Cache (一级数据缓存)";
color=blue;
node [fillcolor=lightgreen];
Cache_Controller [label="Cache Controller (CC)\n(缓存控制器)\n(Hit/Miss Logic, Replacement Policy,\nArray/Buffer Orchestration)"];
Tag_Array [label="Tag Array\n(标签数组)\n(Tag, Valid, Dirty Bits)"];
Data_Array [label="Data Array\n(数据数组)\n(Cache Line Data)"];
Write_Buffer [label="Write Buffer (WB)\n(写缓冲)\n(Store Buffering, Coalescing)"];
MSHRs [label="MSHRs\n(Miss Status Handling Registers)\n(Track Outstanding Misses, Merge)"];
Write_Back_Eviction_Logic [label="Write-Back & Eviction Logic (WBEL)\n(脏行写回, 替换行选择)"];
// LSU initiates requests to Cache Controller using PA
LSU -> Cache_Controller [label="Memory Request (R/W, PA, Data)"];
// Cache Controller orchestrates internal L1D operations
Cache_Controller -> Tag_Array [label="Tag Ops (Compare, R/W Status)"];
Cache_Controller -> Data_Array [label="Data Ops (R/W)"];
Cache_Controller -> MSHRs [label="Initiate Miss Tracking / Allocate MSHR"];
Cache_Controller -> Write_Buffer [label="Submit Write Operation (to WB)"];
Cache_Controller -> Write_Back_Eviction_Logic [label="Trigger Eviction / Write-Back"];
// Feedback from internal components to Cache Controller
Tag_Array -> Cache_Controller [label="Hit/Miss Status, Dirty Status"];
Data_Array -> Cache_Controller [label="Read Data (for Load Hit/Fill)"];
MSHRs -> Cache_Controller [label="Data Ready (Fill Request)"];
Write_Buffer -> Cache_Controller [label="WB Flush Request / Data Ready for Cache"];
Write_Back_Eviction_Logic -> Cache_Controller [label="Victim Line Info / Dirty Data for WB"];
// Cache Controller returns load data to LSU
Cache_Controller -> LSU [label="Load Data"];
}
// 3. System Interconnect & Main Memory
subgraph cluster_interconnect_memory {
label="System Interconnect & Main Memory";
color=darkred;
node [fillcolor=salmon];
Crossbar [label="Crossbar\n(高速互连)"];
Memory_Controller [label="Memory Controller (MC)\n(内存控制器)"];
DRAM [label="DRAM\n(主内存)", shape=cylinder];
L1I_Cache [label="L1I Cache\n(一级指令缓存)", fillcolor=lightgray];
// L1D Cache to/from Crossbar
MSHRs -> Crossbar [label="L1D Miss Request (Read, PA)"];
Write_Back_Eviction_Logic -> Crossbar [label="Dirty Line Write-Back (Write, PA, Data)"];
Crossbar -> MSHRs [label="Data Return (from MC to MSHR)"]; // Data comes back from Crossbar to the MSHR in L1D
// L1I Cache to/from Crossbar
L1I_Cache -> Crossbar [label="L1I Miss Request"];
Crossbar -> L1I_Cache [label="Instruction Data Return"];
// Crossbar to Memory Controller
Crossbar -> Memory_Controller [label="Memory Request (from Caches)"];
Memory_Controller -> Crossbar [label="Data Return (to Caches)"];
// Memory Controller to DRAM
Memory_Controller -> DRAM [label="DRAM Read/Write Commands"];
DRAM -> Memory_Controller [label="Read Data"];
}
}
